I2C Inter Integrated Circuit bus

What Is the I2C Interface?
I2C is an acronym for an Inter-Integrated Circuit bus. I2C is a 2-wire serial interface standard defined by Philips Semiconductor in the early 1980s. Its purpose was to provide an easy way to connect a CPU to peripheral chips in a TV set. The BUS physically consists of 2 active wires and a ground connection. The active wires, SDA and SCL, are both bidirectional. Where SDA is the Serial DAta line and SCL is the Serial CLock line.

The key advantage of this interface is that only two lines (clock and data) are required for full duplexed communication between multiple devices. The interface typically runs at a fairly low speed (100kHz to 400kHz). With I2C, each IC on the bus has a unique address. Chips can act as a receiver and/or transmitter depending on it’s functionality.
The I²C-bus is devoloped by Philips to maximize hardware efficiency and circuit siplicity. The I2C interface is a simple master/slave type interface. Simplicity of the I²C system is primarily due to the bidirectional 2-wire design, a serial data line (SDA) and serial clock line (SCL), and to the protocol format. Bi-directional communication is facilitated through the use of wire and connection (the lines are either active-low or passive high). The I2C Bus protocol also allows collision detection, clock synchronization and hand-shaking for multi-master systems. The clock is always generated by the master, but the slave may hold it low to generate a wait state. In most systems the microcontroller is the master and the external peripheral devices are slaves.
The maximum number of devices connected to the I2C bus is dictated by the maximum allowable capacitance on the lines, 400 pF, and the protocol’s addressing limit of 16k; typical device capacitance is 10 pF. The I2C protocol has 127 addresses available. The original vision was to assign addresses by device function, but when Philips began to sell microcontrollers for I2C, the address could be programmed, eliminating the need for a Philips-assigned address. A device that controls signal transfers on the line in addition to controlling the clock frequency is the master and a device that is controlled by the master is the slave. The master can transmit or receive signals to or from a slave, respectively, or control signal transfers between two slaves, where one is the transmitter and the other is the receiver. I2C bus support more than one master connected to one bus.
The I2C bus is an innovative hardware interface which provides the software designer the flexibility to create a truly multi-master environment. It is possible to combine several masters, in addition to several slaves, onto an I²C-bus to form a multimaster system. If more than one master simultaneously tries to control the line, an arbitration procedure decides which master gets priority.
To begin communication, the bus master (typically a microcontroller) places the address of the device with which it intends to communicate (the slave) on the bus. All ICs monitor the bus to determine if the master device is sending their address. Only the device with the correct address communicates with the master.
Philips’ has over 150 CMOS and bipolair chips who are I²C-bus compatible, and also some other companies make ICs with I2C control interface.
The I2C master is generally implemented with special I2C controller (sometimes integrated to microcontroller) or sometimes using a microcontroller and some software running on it. Both approaches are possible in typical one master I2C system. The multi-master system is not generally implemented with microcontroller software because it is extremely difficult to meet all the I2C Bus timing spec-ifications using software. For a true slave or multi-master system, some interface hardware is necessary (like START & STOP bit detection).

Nowadays there are many different variations of I2C in use. Each of the various I2C derivatives defines a slightly different direct current (DC) electrical interface. I2C by definition is 5V. High and low thresholds, rather than being of fixed value, are a function of VCC for some parts. There are hacks to make I2C to work also on other voltages than 5V. In different application device addrressing can vary. A liberal fixed addressing scheme is quite common (different type of devices get for example four addresses each). ACCESS.bus uses dynamic addressing scheme.
Access.Bus Mouse Application Code For The Microcontroller – pdf file

Analog switch expands I2C interface – This circuit allows connection of the master host to very many I2C devices and prevents the master from addressing multiple slaves at the same time. This circuit allows you to add three times more devices on the bus I2C than is normally possible.
Analog switch frees stuck I²C bus – The dual-channel PCA9540 I2C multiplexer often breaks up an I2C or SM bus or allows you to use devices with the same addresses on the same bus. In same error cases this system can lock up I2C bus. To free up a stuck I2C bus, this circuit controls the supply voltage to force a hardware reset.

AVR302: Software I2C Slave Implementation

Centronics to I2C converter inside DB25 connector

I2C and SMBus framework – Information on I2C and SMBus.

The I2C FAQ – This article is a collection of information sources on the I2C Bus

I2C interfacing via PC parallel port

I2C protocol implementation sources – C source code of I2C driver

I2C Links Interfacing I2C Devices with a PIC16C84 (Interfacing with a Philips PCF8574 8-Bit I/O Expander) – The discussion focuses on the implementation of low level I2C routines which are common to interfacing with most I2C devices. These routines
are discussed in the context of interfacing with an Philips PCF8574 8-bit I/O device. The intent is to illustrate the use of the low level I2C routines.

Software Implementation of I²C Bus Master – This application note describes the software implementation of I2C interface routines for the PIC16CXXX family of devices. Only the master mode of I2C interface is implemented in this application note. This implementation is for a single master communication to multiple slave I2C devices. In addition to the low level single master I2C routines, a collection of high level routines with various message structures is given. These high level macros/routines can be used as canned routines to interface to most I2C slave devices. As an example, the test program talks to two Serial EEPROMs (Microchip.s 24LC04 and 24LC01).

The I2C-bus and how to use it (including specifications)

Software reset uses I²C I/O port – You can use this circuit to allow the I2C or SMBus to control device resets in a system by using the PCA9554 I2C I/O-port IC.

The I 2 C serial bus: theory and practical consideration using Philips low-voltage PCF84Cxx and PCD33xx mC families (AN168)

The I2C-Bus Specification Version 2.1 January 2000

Two-transistor circuit replaces IC – Linear Technology’s recently introduced LTC4300 chip buffers I2C clock and data lines to and from a hot-swappable card. This task is difficult because the IC must work bidirectionally, meaning that you can simultaneously and actively drive both sides. However, as is sometimes the case, you can replace a complicated circuit by a simple one without much loss of performance. For example, transistors and resistors replace the entire IC. Two npn transistors, connected head-to-head, form the heart of the circuit. The two-transistor circuit offers the additional benefit of acting as a level translator between two logic levels, for example 3.3V and 5V. More on two-transistor circuit – Information on two-transistor logic level translator circuit